Complementary Metallic Oxide Semiconductor (CMOS) integrated circuit technology is relatively inexpensive, and it allows designers to include some digital logic circuitry and some analog circuitry in the same integrated circuit. Using this technology, designers have implemented analog-to-digital converter integrated circuits, which measure an analog voltage and convert it to a corresponding digital representation. Because it is generally difficult to produce accurate resistors using CMOS technology, the technique of charge redistribution, which uses capacitors instead of resistors, has been used in some CMOS analog-to-digital converters.
Referring to FIG. 1, a simple six-bit analog-to-digital converter circuit which uses the prior art technique of charge redistribution includes an array of binary-weighted capacitors C0-C5. These capacitors have one terminal commonly connected to the non-inverting input (+) of a comparator CP, and this comparator input is also connected to a grounding switch SA. A series of array switches S0-S5 can individually connect the other terminal of each of the capacitors either to ground or to an input node IN. An input switch SB can, in turn, switch the input node between an input voltage Vin and a reference voltage Vref.
The circuit performs an analog-to-digital conversion in a three-step operation. First is a sampling step in which the common terminal of the capacitors is grounded by the grounding switch SA, and the second terminal of each of the capacitors is connected to the input voltage via the array switches S0-S5 and the input switch SB. At the end of this first step, the capacitors collectively store a charge proportional to the input voltage.
A holding step follows the sampling step. In this holding step, the common switch SA opens so that the common terminals of the capacitors are no longer grounded, and the series of switches S0-S5 are actuated so that the second terminals of the capacitors are grounded. During the holding step, the voltage at the first terminal of the capacitors, which is presented to the comparator, is equal to the input voltage.
The third step is a charge redistribution step, in which the input switch connects the input node to the reference voltage Vref, and the circuit iteratively derives a digital representation of the analog input voltage. In a first iteration, the first array switch SO switches the second terminal of the largest capacitor in the array CO (corresponding to the most significant bit or "MSB") from ground to the reference voltage. This creates a voltage divider between two essentially equal capacitances, which sets the voltage measured by the comparator equal to about half of the difference between the reference voltage and the input voltage.
If the comparator detects a voltage above ground in this first iteration, the bit corresponding to the first capacitor (MSB) is set to zero (in logic circuitry receiving the output of the comparator, but not shown, for simplicity). Conversely, if the voltage detected at the comparator input is below ground, the bit is set to one. The first array switch SO then grounds the second terminal of the MSB capacitor C0, but only if the comparison resulted in a digital bit value of zero. The circuit repeats these voltage divider operations in succession for each capacitor until capacitor C5, corresponding to the least significant bit (LSB), has been tested. The entire three-step conversion process can then start again with a second sampling step.
In a modified version of this circuit, the voltage supplied to the comparator ranges from ground to the reference voltage, rather than varying above and below ground by the reference voltage. This modification can be achieved by supplying Vin to the non-inverting input of the comparator through a sampling capacitor, instead of supplying it as an alternative to the reference voltage. In addition, the inverting input of the comparator is set to a potential half way between ground and the reference voltage.
A different operating sequence allows these types of converters to perform bipolar measurements. This sequence begins with the second terminal of the largest capacitor connected to the reference voltage during the sampling step. The circuit then tests each bit in the same manner as is described above, except that the first array switch switches the largest capacitor from the reference voltage to ground during its test instead of switching it from ground to the reference voltage. If the comparator detects a negative voltage on any of the tests, the corresponding bit is set to one, as described above. The resulting digital value is a 1's complement number, which can be either negative or positive, depending on the value of the most significant bit. In essence, this mode of operation employs the largest capacitor to level shift the voltage at the input to the capacitor.
These prior art charge redistribution techniques are well suited for operation with a system using split voltage supplies. They are not optimum, however, for a system that uses a single supply, particularly a single low-voltage supply.
In "Adaptive Reference Voltage Adjustment for an Analog-to-Digital Converter," IBM Technical Disclosure Bulletin, Vol. 19, No. 6, November 1976, Y. S. Yee proposes to adaptively adjust the reference voltage of an analog-to-digital converter by providing an on-chip continuously self-calibrating subsystem. This subsystem provides a second weighted capacitor ladder in the feedback path of an amplification circuit on the output of the converter's main capacitor ladder. This second ladder is adjusted to compensate for differences in the reference voltage during a calibration operation. This is said to enable the analog-to-digital converter to operate without a precision reference voltage supply, and to eliminate the need for potentiometer adjustment calibrations.
The Yee system does not, however, permit calibration for both gain and offset errors.